Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority of Japanese PatentApplication No. 2008-96800 filed on Apr. 3, 2008, the entire contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing the same, and more particularly to a semiconductor devicehaving a wiring board for use in mounting a semiconductor element or thelike, and a method of manufacturing the same.

Note that the “wiring board” is hereinafter also referred to as a“semiconductor package” or merely a “package” for the sake ofconvenience, because the wiring board plays the role of mounting asemiconductor element or the like thereon.

(b) Description of the Related Art

A semiconductor package such as a ball grid array (BGA), a land gridarray (LGA) or a pin grid array (PGA) generally has a multilayer wiringstructure. The multilayer wiring structure is obtained, for example, bybuild-up process sequentially repeating the formation of a conductivepattern (wiring layer), the formation of an insulating layer, and theformation of a via hole in the insulating layer, on both surfaces of acore board provided as a base material for the semiconductor package.Finally, the outermost wiring layer is coated with a protection film,and an opening is formed at a required position in the protection filmwhile a portion of the conductive pattern is exposed as a pad portion.In the case of the BGA or the PGA, a ball, a pin or the like whichfunctions as an external connection terminal is further bonded to theexposed pad portion.

A semiconductor package of this type has a semiconductor element such asan IC chip mounted on a surface thereof with a conductive material suchas solder therebetween. The semiconductor package with the semiconductorelement mounted thereon is then packaged on a packaging object such as amotherboard or a socket component with an external connection terminal(such as a ball or a pin) therebetween, the external connection terminalprovided on the other surface of the semiconductor package. Namely, thesemiconductor element is electrically connected to the motherboard orthe like with the semiconductor package therebetween.

Meanwhile, as demands for miniaturization and multiple functions inelectronic equipment or an electronic device grow recently, asemiconductor device for use in the electronic equipment or theelectronic device has been smaller in size, higher in packaging density,and higher in pin count (higher in terminal count). With this demand, asemiconductor device, called a chip size package or a die size package,has been developed and come into practical use, which is designed toachieve miniaturization by bringing the shape of the semiconductordevice as close to that of an individual semiconductor element (chip) aspossible.

An example of technology related to the above-mentioned prior art isdescribed in Japanese unexamined Patent Publication (JPP) (Kokai)8-167629. This publication discloses a semiconductor device, whichincludes a sealing resin to seal a semiconductor substrate, a leadpattern transferred to the underside of the sealing resin, and aplurality of external electrodes formed on the underside of the leadpattern.

Of the prior art semiconductor packages as mentioned above, the chipsize package (die size package) has attracted attention in the course ofdevelopment of recent downsizing; however, such a chip size package maypossibly be deficient in the number of terminals under restrictions on achip (die) size and a terminal pitch.

Namely, the increase in integration density per chip leads to theincrease in the number of inputs and outputs, and to a need for a largernumber of external connection terminals. A semiconductor package havingan active IC chip such as a microprocessor unit (MPU) mounted thereon,in particular, requires a significantly larger power supply current. Forthis reason, a larger number of external connection terminals areassigned to the power supply to the chip in the semiconductor package,which account for more than half of the total terminals of the package.Namely, only less than half terminals thus left are available as inputsand outputs for signals.

On the other hand, the miniaturization of the package leads to a limitednumber of external connection terminals which can be built in thepackage. Accordingly, under the current circumstances, the prior artchip (die) size package has difficulty in ensuring a sufficient numberof external connection terminals.

Furthermore, the mounting of the semiconductor element such as an ICchip on the semiconductor package involves: connecting an electrodeterminal of the chip to the pad portion exposed on the chip mountingsurface of the package, by flip chip bonding, using a conductivematerial such as solder; filling an underfill resin into a gap betweenthe package and the chip; and heat-curing and thus setting the resin. Atthe time of heat curing, a difference in the coefficient of thermalexpansion between the resin and the board causes a shrinkage in theunderfill resin, resulting in warpage in the package affected by theshrinkage.

To reduce such “warpage” resulting from a cure shrinkage in theunderfill resin at the time of chip mounting, the package (wiring board)needs to be configured in a considerable thickness (i.e. in multiplelayers). Also, such a package generally has a multilayer structure underrestrictions on the width of a wiring pattern or a via contact(interlayer connection) and thus has disadvantage of impairing thethinning (miniaturization) of the overall package.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor deviceand a method of manufacturing the same, which satisfies, when needed, aneed to increase the number of external connection terminals with ademand for a high packaging density or the like, and can eliminate awarpage of a package, while achieving miniaturization.

According to one aspect of the invention, there is provided asemiconductor device including: a semiconductor element; a laminatedwiring structure formed integrally with the semiconductor element; aframe disposed to surround the semiconductor element on the laminatedwiring structure, and made of a material having stiffness; and a sealingresin formed to bury therein the frame and at least the periphery of aside surface of the semiconductor element, wherein the laminated wiringstructure includes a required number of wiring layers, and the wiringlayers are formed by patterning in such a manner that a wiring patterndirectly routed from an electrode terminal of the semiconductor elementis electrically connected to pad portions for bonding externalconnection terminals, the pad portions being provided, at a positiondirectly below a mounting area of the semiconductor element and at aposition directly below an area outside the mounting area, on a surfaceto which the external connection terminals are bonded.

According to the configuration of the semiconductor device of thepresent invention, the laminated wiring structure formed integrally withthe semiconductor element functions as a package mounting thesemiconductor element thereon, and the wiring layers which constitutethe package are formed by patterning in such a manner that the wiringpattern directly routed from the electrode terminal of the semiconductorelement is electrically connected to pad portions for bonding externalconnection terminals, the pad portions being provided, at a positiondirectly below a mounting area of the semiconductor element and at aposition directly below an area outside the mounting area, on thesurface to which the external connection terminals are bonded. Even ifthere arises a need to increase the number of external connectionterminals with a demand for high packaging density or the like, such aconfiguration of the package is sufficiently adaptable to the demand.

Also, the frame made of the material having stiffness is disposed tosurround the semiconductor element so that the stiffness of the overallpackage is improved. Accordingly, a disadvantage of the package becoming“warped”, such as encountered in the prior art, does not arise.Moreover, the package is prevented from being warped without having themultilayer structure as has been conventional, and thus thinning(miniaturization) of the package can be achieved.

According to another aspect of the invention, there is provided a methodof manufacturing a semiconductor device, including the steps of:preparing a plate-shaped frame attached to a tape-shaped base material,the frame being made of a material having stiffness, and having anopening of a required size formed therein; mounting a semiconductorelement in a face-down mounting manner, on a portion corresponding tothe opening in the frame on the tape-shaped base material; sealing theframe and at least the periphery of a side surface of the semiconductorelement with a sealing resin; removing the tape-shaped base material;forming a wiring pattern to be directly connected to an electrodeterminal of the semiconductor element, and thereafter stacking arequired number of wiring layers one on top of another, the requirednumber of wiring layers being formed by patterning in such a manner thatthe wiring pattern is electrically connected to pad portions for bondingexternal connection terminals, the pad portions being provided, at aposition directly below a mounting area of the semiconductor element andat a position directly below an area outside the mounting area, on asurface to which the external connection terminals are bonded; andforming a protection film to expose the pad portions for bondingexternal connection terminals.

With reference to the following embodiments of the invention,description is given below of other features in configuration of thesemiconductor device and the method of manufacturing the same accordingto the present invention, characteristic advantages based on thefeatures thereof, and so on.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing the configuration of a semiconductordevice provided with a package having a fan-out structure according toone embodiment of the present invention;

FIGS. 2A to 2E are sectional views illustrating an example of amanufacturing process for the semiconductor device shown in FIG. 1;

FIGS. 3A to 3D are sectional views illustrating a manufacturing processfollowing the process shown in FIGS. 2A to 2E;

FIGS. 4A to 4E are sectional views illustrating another example of amanufacturing process for the semiconductor device shown in FIG. 1; and

FIG. 5 is a sectional view illustrating an example of application of thesemiconductor device shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Description is given below of preferred embodiments of the presentinvention with reference to the accompanying drawings.

FIG. 1 shows in sectional view the configuration of a semiconductordevice provided with a package having a fan-out structure according toone embodiment of the present invention.

A semiconductor device 10 according to the embodiment of the presentinvention is basically provided with a chip 20 (typically, a silicon(Si) chip) such as a semiconductor element, a laminated wiring structure30 provided integrally with the chip 20, a frame 40 disposed on thelaminated wiring structure 30 to surround the periphery of the sidesurface of the chip 20, and a sealing resin 41 formed to coat theoverall surface of the frame 40 and the periphery of the side surface ofthe chip 20 (or to bury the overall chip 20 therein).

The semiconductor chip 20 built in the semiconductor device 10 is a chip(also referred to as “die”) obtained by dicing, in units of device, awafer having a plurality of devices fabricated therein using a processfor a wafer level package, as described later.

The laminated wiring structure 30 is functionally equivalent to a“wiring board (package)” or an “interposer” as having the roll to allowthe semiconductor chip 20 to be mounted thereon as shown in FIG. 1. Thelaminated wiring structure 30 has a structure in which wiring layers(wiring layers 32, 34 and 36 in the example shown in FIG. 1) as many asnecessary are stacked one on top of another with insulating layers 31,33 and 35 interposed therebetween and the stacked wiring layers areinterconnected with conductors (which are formed by part of materialincluded in the wiring layers 32, 34 and 36) filled into via holesformed in the insulating layers 31, 33 and 35 interposed therebetween.The innermost wiring layer (the uppermost wiring layer 32 in the exampleshown in FIG. 1) of the laminated wiring structure 30 is directly routedfrom an electrode terminal 21 (such as a solder bump or a gold (Au)bump) of the semiconductor chip 20 mounted on the laminated wiringstructure 30. Namely, the wiring layer 32 is formed by patterning to beconnected to the electrode terminal 21. Copper (Cu) is typically used asa material for the wiring layers 32, 34 and 36, and an epoxy resin, apolyimide resin or the like is used as a material for the insulatinglayers 31, 33 and 35.

Also, the outermost wiring layer (the lowermost wiring layer 36 in theexample shown in FIG. 1) of the laminated wiring structure 30 has padportions 36P defined at predetermined positions. The pad portions 36Pare disposed as shown in FIG. 1, not only on a portion directly below achip mounting area but also on a portion corresponding to an areaoutside the portion directly below the chip mounting area. Moreover, asolder resist layer 37 is formed as a protection film to coat thesurface of the laminated wiring structure 30 with the pad portions 36Pbeing exposed.

The pad portion (Cu) 36P is plated with nickel (Ni) and gold (Au) inthis order, since an external connection terminal 38 such as a solderball for use in mounting the device 10 on a printed wiring board (i.e.,a packaging board) such as a motherboard is bonded to the pad portion36P exposed from the solder resist layer 37. This is for the purpose ofimproving contact bonding properties when the external connectionterminal 38 is bonded to the pad portion 36P (i.e., Au layer), and forthe purpose of enhancing adhesion between the Au layer and the padportion (Cu) 36P and thereby preventing Cu from diffusing into the Aulayer (i.e., Ni layer). Namely, the pad portion 36P has a three-layerstructure of Cu, Ni and Au.

Incidentally, the external connection terminal 38 is provided on the padportion 36P in the illustrated example; however, the provision of theexternal connection terminal 38 is not necessarily required. It issufficient only that the pad portion 36P be exposed so as to allow theexternal connection terminal to be bonded thereto when necessary.

As mentioned above, the laminated wiring structure 30 is used forproviding alignment (rewiring) between the electrode terminals 21 of thesemiconductor chip 20 mounted thereon and the external connectionterminals 38 to be connected to the motherboard or the like, and has aform, a so-called “fan-out structure”, in which an area of the externalconnection terminals 38 is extended around the chip mounting area asshown in FIG. 1. Namely, the external connection terminals 38 areprovided in a “grid array” form throughout the entire mounting surfaceof the device 10.

On the other hand, the frame 40 disposed around the chip 20 on thelaminated wiring structure 30 is made of a material having sufficientmechanical strength (stiffness), as functioning as a stiffener (areinforcing member) to prevent warpage in the device 10 (specifically,the laminated wiring structure 30), as described later. Preferably, itis desirable that the frame 40 be made of a material having a lowcoefficient of thermal expansion. For example, iron (Fe) or an alloythereof (such as an alloy of 42% nickel (Ni) and Fe), copper (Cu) or analloy thereof (such as an alloy of Cu, iron (Fe) and phosphorus (P)), orthe like, which are generally used as a base material for a lead framecan be used. A glass epoxy resin which constitutes a core material for abuild-up wiring board, or the like may be used in place of such a metalmaterial.

The sealing resin 41 formed to coat the frame 40 and the periphery ofthe side surface of the semiconductor chip 20 (or to bury the overallchip 20 therein) is used for keeping and fixing an integral structure ofthe chip 20, the laminated wiring structure 30 and the frame 40. Athermosetting epoxy resin generally used as a molding resin, a liquidepoxy resin generally used as an underfill resin, or the like, forexample, can be used as a material for the sealing resin 41.

As mentioned above, the semiconductor device 10 according to the presentembodiment is characterized in that: the device 10 is in such a formthat the semiconductor chip 20 is integral with the laminated wiringstructure 30 functioning as the package; the chip 20 is buried in thesealing resin 41 to have a surface exposed, the surface being oppositeto that on which the electrode terminals 21 of the chip 20 are formed(or the overall chip 20 is buried in the sealing resin 41); and further,a wiring pattern is directly routed from the electrode terminal 21 ofthe chip 20 and the external connection terminals 38 (the pad portions36P) are disposed not only on the portion directly below the chipmounting area but also on the portion corresponding to the area outsidethe portion directly below the chip mounting area with the rewiring bythe laminated wiring structure 30. Moreover, the semiconductor device 10is characterized in that the frame 40 (the stiffener) is disposed tosurround the periphery of the side surface of the chip 20 on the package(namely, the laminated wiring structure 30).

Next, description is given of a method of manufacturing thesemiconductor device 10 according to the present embodiment (FIG. 1)with reference to FIGS. 2A to 2E and FIGS. 3A to 3D showing an exampleof a manufacturing process for the semiconductor device 10. Note that,in sectional views showing steps of FIG. 3A and the following drawings,part of the configuration shown in FIG. 1 (namely, a portion of thelaminated wiring structure 30) is shown in simplified form.

First, at the first step (see FIG. 2A), prepared is the frame 40 havingan opening OP larger than the size (die size) of the chip to be mounted.Any material may be used as the material for the frame 40, as far as thematerial has sufficient mechanical strength (stiffness) as well as a lowcoefficient of thermal expansion, as mentioned above. For example,prepared is a thin plate of copper (Cu) used as the base material forthe lead frame, and the rectangular opening OP of the required size isformed in the metal (Cu) plate by pressing or etching. In the exampleshown in FIG. 2A, only one opening OP (one frame 40) is shown for thesake of simplicity; however, a plurality of openings OP (a plurality offrames 40) are actually arranged.

Then, the frame 40 prepared in this manner is attached to the surface ofa base material (e.g., a tape 50 such as a polyimide resin) to which anadhesive is applied, the base material being shaped in tape form withthe adhesive applied on one surface. The tape 50 functions as a basematerial to temporarily allow the chip 20 to be mounted thereon at adefined position as described later.

At the next step (see FIG. 2B), a silicon chip 20 fabricated in advanceat a different step is mounted on the tape 50 in a portion correspondingto the opening OP in the frame 40, in such a manner that a surface whichconstitutes a circuit (i.e., the surface on which the electrodeterminals 21 are formed) is faced down, i.e., in a face down mountingmanner (i.e., die attach).

A process for a wafer level package can be used to fabricate the chip 20to be mounted. The chip (die) 20 with the electrode terminals 21 exposedon one surface as shown in FIG. 2B can be obtained, for example, in thefollowing manner. Specifically, one surface of a silicon wafer of apredetermined size (e.g., 8 inches or 12 inches) is subjected to arequired device process to make an array of a plurality of devices; apassivation film made of silicon nitride (SiN), phosphorus glass (PSG)or the like is formed on the surface on which the devices are formed; bya laser or the like, the passivation film is partially removed at aportion corresponding to a pad (the electrode terminal 21) defined inpart of a wiring layer of aluminum (Al) shaped in a required pattern oneach device; the wafer is thinly grinded to a predetermined thickness;and then the wafer is diced into units of devices by a dicer or thelike.

At the time of dicing the wafer into units of devices, the wafer ismounted on a dicing tape supported on a dicing frame, with a die attachfilm interposed therebetween, with the surface of the wafer opposite tothat on which the devices are formed, attached to the dicing tape. Thewafer is then cut by a blade of the dicer along a line which defineseach device region, and thereafter, the cut and divided chips (dies) 20are picked up. At that time, each individual chip (die) 20 has the dieattach film attached thereto; however, illustration of the die attachfilm is omitted in the example shown in FIG. 2B.

At the time of mounting the chip (die) 20 at the defined position on thetape 50, for example, an alignment mark previously given to the frame 40is read by a microscope or the like, and the chip 20 is mountedaccording to the detected position.

At the next step (see FIG. 2C), the chip 20 is sealed by a sealing resin41 so that the frame 40 attached to the tape 50 and the periphery of theside surface of the mounted chip 20 are coated with the sealing resin41. This can be accomplished using a mold (a top force and a bottomforce) to perform compression molding by heat and pressure.

The thermosetting epoxy resin used as the molding resin, the liquidepoxy resin used as the underfill resin, or the like can be used as thematerial for the sealing resin 41. Also, the sealing resin 41 is notlimited to a liquid form, but may be in a tablet or a powder form.Transfer molding, injection molding, potting, or the like can beemployed as a filling method for the sealing resin 41, Alternatively,printing may be employed to apply a coating method of a paste resin.

Incidentally, where the sealing resin 41 partially remains on the backsurface of the chip 20 (i.e., on the surface opposite to that on whichthe electrode terminals 21 are formed) when being filled at the step ofFIG. 2C, the resin surface may be polished, for example, by mechanicalpolishing to thereby expose the back surface of the chip 20.

Also, in the step of FIG. 2C, resin sealing is performed in such amanner that the back surface of the chip 20 is exposed; however, theexposure of the back surface of the chip 20 is not necessarily required,depending on the amount of power consumed by a chip to be mounted. Forexample, where the chip to be mounted is one which consumes less power,unlike a microprocessor unit (MPU), the chip produces only a smallamount of heat, and thus the overall chip may be buried in the resinfrom the viewpoint of chip protection.

At the next step (see FIG. 2D), the tape 50 (see FIG. 2C) made ofpolyimide resin or the like utilized as the base material to temporarilyallow the chip 20 to be mounted thereon is delaminated and removed. Atthis stage, a portion of the adhesive applied to the delaminated tape 50can possibly remain on the surface of the chip 20 on which the electrodeterminals 21 are formed (on the lower surface in the illustratedexample).

At the next step (see FIG. 2E), the possible remaining adhesive isremoved, for example, by ashing (i.e., dry etching using O₂ plasma).Thereby, the electrode terminals 21 of the chip 20 as well as the frame40 are exposed.

At the next step (see FIG. 3A), an insulating layer 31 is formed on thesurface on which the electrode terminals 21 of the chip 20 and the frame40 are exposed, and an opening VH is formed at a predetermined position.The insulating layer (polyimide resin layer) 31 having the opening VH atthe predetermined position as shown in FIG. 3A is formed in a followingmanner. Specifically, a photosensitive polyimide resin is applied to thesurface of the chip 20 on which the electrode terminals 21 are formed,by photolithography; the polyimide resin is subjected to soft baking(pre-baking); then exposure and development (i.e., patterning of thepolyimide resin layer) is performed using a mask (not shown); andfurther, hard baking (post-baking) is performed. At that time, thepatterning of the polyimide resin layer is performed according to thelayout (arrangement) of the electrode terminals 21 of the chip 20.Therefore, when the exposure and the development are performed, aportion of the polyimide resin layer 31 corresponding to the electrodeterminal 21 is removed, so that the opening VH reaching the electrodeterminal 21 is formed.

At the next step (see FIG. 3B), a wiring layer (pattern) 32 of arequired shape is formed by semi-additive process or the like so as tofill the opening VH and to be connected to the electrode terminal 21. Aspecific example is described below.

First, a seed layer is formed over the entire surface on which theinsulating layer 31 is formed, by sputtering, electroless plating, orthe like. For example, the seed layer of a two-layer structure can beformed by sputter-depositing chromium (Cr) or titanium (Ti) over theentire surface (a contact metal layer, i.e., a Cr layer or a Ti layer),and further, sputter-depositing copper (Cu) on the Cr or Ti layer. Then,the surface of the seed layer (i.e., the surface of the Cu layer) isdehydrated and baked; a liquid photoresist is applied and dried; andthen exposure and development (i.e., patterning of the photoresist) isperformed using a mask (not shown) to thereby form a resist layer. Thepatterning of the photoresist is performed according to the layout ofthe wiring pattern to be formed. Instead of the liquid photoresist, aphotosensitive dry film may be attached and subjected to patterning.

Subsequently, a Cu wiring layer (rewiring layer) 32 is formed in arequired form by Cu electroplating utilizing the seed layer as a powerfeed layer, using as a mask the resist layer formed by patterning.Thereafter, the photoresist is removed using a remover containing anorganic solvent. Where a dry film is used in place of the photoresist,an alkaline chemical liquid such as sodium hydroxide (NaOH) ormonoethanolamine is used to delaminate and remove the dry film.

Moreover, the exposed seed layer is removed by wet etching. In thiscase, first, the Cu layer in an upper layer portion of the seed layer isremoved by an etchant which dissolves Cu, and then, the contact metallayer (i.e., the Cr layer or the Ti layer) in a lower layer portionthereof is removed by an etchant which dissolves Cr or Ti. Thereby, theinsulating layer 31 is exposed as shown in FIG. 3B. Thereafter,predetermined surface cleaning or the like is performed.

Incidentally, when the etchant which dissolves Cu is used, it seems thatCu which forms the rewiring layer 32 is also removed and the pattern isdisconnected; however, such a disadvantage does not actually arise. Thereason is as follows: as mentioned above, the upper layer portion of theseed layer is formed by Cu sputtering and thus has a layer thickness ofthe submicron order, while the rewiring layer 32 is formed by Cuelectroplating and thus has a layer thickness of the order of at least10 μm. Accordingly, even if Cu of the seed layer is completely removed,the rewiring layer 32 (Cu) only has its top surface portion removed, sothat the rewiring pattern is not disconnected.

After the wiring layer 32 to be connected to the electrode terminals 21of the chip 20 is formed by filling the opening VH as mentioned above,the like processes as those performed at the steps of FIGS. 3A and 3Bare repeated to stack the insulating layers 33 and 35 and the wiringlayers 34 and 36 alternating with each other, one on top of another,until the required number of layers is reached, to thereby form thelaminated wiring structure 30 (see FIG. 1).

At the next step (see FIG. 3C), the solder resist layer 37 is formed bycoating the entire surface so that the pad portions 36P defined at thepredetermined positions on the outermost wiring layer 36 are exposed.Moreover, the exposed pad portions 36P are plated with Ni and Au.

At the final step (see FIG. 3D), a flux serving as a surface treatmentagent is applied to the pad portions 36P exposed from the solder resistlayer 37, and then solder balls for use as the external connectionterminals 38 are mounted and are fixed by reflow soldering at atemperature of 240 to 260 degrees. Thereafter, the flux is removed bycleaning the surface.

Moreover, the wafer is divided into units of individual devices (each ofwhich is a portion including one chip 20 and the frame 40 disposedaround the chip 20) by the dicer or the like, to obtain thesemiconductor device 10 (FIG. 1) according to the present embodiment.

As described above, according to the semiconductor device 10 (FIG. 1) ofthe present embodiment and the method of manufacturing the same (FIGS.2A to 2E and FIGS. 3A to 3D), the laminated wiring structure 30 formedintegrally with the semiconductor chip 20 functions as the package whichallows the chip 20 to be mounted thereon, and the required number of thewiring layers 32, 34 and 36 which constitute the package are formed bypatterning in such a manner that the wiring pattern (the wiring layer32) directly routed from the electrode terminal 21 of the chip 20 iselectrically connected to the external connection terminals 38 (the padportions 36P) provided both on the portion directly below the chipmounting area and on the portion corresponding to the area outside theportion directly below the chip mounting area. Such a configurationenables achieving the package of the fan-out structure (i.e., thelaminated wiring structure 30) which has been unfeasible with the priorart die size package. Therefore, even if there arises a need to increasethe number of external connection terminals with the demand for highpackaging density and multiple terminals, the device and the method ofthe present invention are sufficiently adaptable to the need.

Also, a thin film wiring rule (the process for the wafer level package)can be used to form the wiring layers 32, 34 and 36 which constitute thelaminated wiring structure 30, which facilitates fine wiring and thusenables minimizing the number of layers. This contributes to a thinningof the package and hence to miniaturization of the package.

In addition, the frame 40 having sufficient mechanical strength isdisposed to surround the periphery of the side surface of the mountedchip 20, and the frame 40 and the chip 20 are buried and fixed in thesealing resin 41. Accordingly, the stiffness of the overall package isimproved. Thereby, for example, when the device 10 is mounted on theinterposer or the like, even if stress is produced at an interfacebetween the device and the interposer, depending on a difference in thecoefficient of thermal expansion between the device and the interposer,incident to the heat curing of the underfill resin filled into a gapbetween the device and the interposer, the frame 40 interposedtherebetween reinforces the overall package and thus eliminates adisadvantage of the package becoming “warped.”

Additionally, the back surface of the mounted chip 20 (i.e., the surfaceopposite to that on which the electrode terminals 21 are formed) isexposed, and thus, heat produced by the chip 20 can be dissipateddirectly to the outside, which is advantageous in a heat dissipationeffect. This is effective in particular when a chip which consumes highpower, such as a microprocessor unit (MPU), is mounted.

In the method of manufacturing the semiconductor device 10 according tothe above-mentioned embodiment (see FIGS. 2A to 2E and FIGS. 3A to 3D),when at the die attach step (FIG. 2B), the chip (die) 20 is mounted atthe defined position on the tape 50, the alignment mark given to thecopper (Cu) plate (the frame 40) serving as the base material for thelead frame is read by the microscope or the like in order to align thechip 20; however, the alignment mark on a member such as the copper (Cu)plate which is an object to which the mark is given is not necessarilyread with high accuracy when the position of the mark is read by themicroscope or the like. In view of this, with reference to FIGS. 4A to4E, description is given of an embodiment in which improvement is madeon this respect.

FIGS. 4A to 4E show another example of a manufacturing process for thesemiconductor device 10 (FIG. 1) according to the present embodiment,and correspond to the steps shown in FIGS. 2A to 2E.

A manufacturing method according to the improved embodiment (FIGS. 4A to4E) is different from the manufacturing method according to theabove-mentioned embodiment (FIGS. 2A to 2E) in the following points.Specifically, the different points are: at the first step (see FIG. 4A),when the frame 40 having the opening OP is attached to the tape 50 suchas polyimide resin, a base material 51 (e.g., a silicon board, a glassboard, or the like) having a highly accurate alignment pattern AP (e.g.,1 μm or less) previously formed thereon by using a thin film wiringprocess is disposed under the tape 50; at the next step (see FIG. 4B),when the die attach is performed, the alignment pattern AP through whichthe tape 50 can be seen is read by the microscope or the like, and thechip (die) 20 is mounted according to the pattern position; and at thestep shown in FIG. 4D, when the tape 50 is delaminated, the basematerial 51 with the alignment pattern AP is also delaminated. Sinceother steps are the same as those of the manufacturing method accordingto the above-mentioned embodiment (see FIGS. 2A to 2E and FIGS. 3A to3D), description thereof is omitted.

According to the manufacturing method shown in FIGS. 4A to 4E, the highaccurate alignment pattern AP formed using the thin film wiring processis read to align the chip 20, and thus the manufacturing method furtherhas an advantage of enabling the high-accuracy arrangement of the chips20 to be mounted on the tape 50, in addition to the advantageous effectsachieved by the manufacturing method according to the above-mentionedembodiment (see FIGS. 2A to 2E and FIGS. 3A to 3D).

FIG. 5 shows an example of application of the semiconductor device 10(FIG. 1) including the package (i.e., the laminated wiring structure 30)having the fan-out structure according to the above-mentionedembodiment, and shows the configuration (sectional structure) of thesemiconductor device 10 when mounted on an interposer 60.

In the configuration of the interposer 60 shown in FIG. 5, wiring layers62 and 63 are formed on both surfaces of an insulating base material 61,and the wiring layers 62 and 63 are interconnected via through holesformed at required positions in the insulating base material 61(conductors filled into the through holes). Moreover, insulating layers64 and 65 are formed on the insulating base material 61 and the wiringlayers 62 and 63, and further, wiring layers 66 and 67 formed on theinsulating layers 64 and 65 are connected with each other via conductors(which are formed by part of material which is included in the wiringlayers 66 and 67, respectively) filled into via holes formed in theinsulating layers 64 and 65. Namely, the interposer 60 has a structurein which the four wiring layers 62, 63, 66 and 67 are stacked one on topof another.

Additionally, a pad portion 66P is defined on the surface of the wiringlayer on which the semiconductor device 10 is mounted (in the uppermostwiring layer 66 in the illustrated example), at a position correspondingto the position of the external connection terminal (the solder bump orthe like) 38 of the semiconductor device 10, and a pad portion 67P isdefined on the lowermost wiring layer 67 which is the opposite surfacethereof, at a position corresponding to the position of a connectionterminal (not shown) such as a solder bump for use in mounting on themotherboard or the like. Also, protection films (solder resist layers)68 and 69 are formed on both surfaces of the interposer 60 to coat theentire surface but to expose the pad portions 66P and 67P of the wiringlayers 66 and 67, and further, the pad portions 66P and 67P of thewiring layers exposed from the protection films 68 and 69 are platedwith Ni and Au.

This structure (FIG. 5) can achieve the following advantages.Specifically, as previously mentioned, in the structure of the prior artpackage (wiring board or interposer), the package needs to have aconsiderable thickness (multiple layers) in order to reduce “warpage”resulting from a cure shrinkage in the underfill resin at the time ofchip mounting, and also, the package generally has a multilayerstructure under restrictions on the width of the wiring pattern or a viacontact, in order to achieve the fan-out structure required for thepackage.

On the other hand, in the configuration of the semiconductor device 10according to the present embodiment, as mentioned above, the wiringpattern (the wiring layer 31) is directly routed from each electrodeterminal 21 of the semiconductor chip 20, and the routed wiring patternsare connected to the external connection terminals 38 or the padportions 36P provided not only on the portion directly below the chipmounting area but also on the portion corresponding to the area outsidethe portion directly below the chip mounting area by the rewiring in thelaminated wiring structure 30 (i.e., the fan-out structure). Therefore,when the semiconductor device 10 having such a fan-out structure builttherein is connected to the interposer, the semiconductor device 10 canbe connected to the interposer 60 having at most a four-layer structuresuch as shown in FIG. 5, so that the required fan-out structure can beachieved. Namely, the configuration shown in FIG. 5 eliminates a needfor the package having a multilayer wiring structure such as has beenconventional, and thus enables contributing to reductions inmanufacturing cost as well as in manufacturing time.

1. A semiconductor device comprising: a semiconductor chip includingelectrode terminal bumps; a laminated wiring structure formed integrallywith the semiconductor chip in direct contact with the electrodeterminal bumps; a frame disposed to surround the semiconductor chip onthe laminated wiring structure, and made of a material having stiffness;and a sealing resin formed to bury therein the frame and at least theperiphery of a side surface of the semiconductor chip, wherein a sidesurface of the laminated wiring structure is exposed from the sealingresin; wherein electrical paths extend from the electrode terminal bumpsof the semiconductor chip to respective pad portions, the pad portionsare located on a surface of the laminated wiring structure distal fromthe semiconductor chip, and the electrical paths consist of wiringinternal to the laminated wiring structure; wherein the sealing resin isformed to coat a top surface and an inner side surface of the frame, anda side surface of the semiconductor chip, and to expose a surface of thesemiconductor chip opposite to a surface thereof on which the electrodeterminals are formed; and wherein an uppermost insulating layer of thelaminated wiring structure is directly disposed on the surface of thesemiconductor chip on which the electrode terminals are formed, and eachof the electrode terminals is connected to a wiring layer which isformed to fill a corresponding via hole formed in the uppermostinsulating layer.
 2. The semiconductor device according to claim 1,comprising external connection terminals bonded to the pad portions. 3.The semiconductor device according to claim 1, wherein the frame isconstituted of glass epoxy resin.